View MAX2769BETIV_6518892.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

max2769b universal gps receiver ????????????????????????????????????????????????????????????????? maxim integrated products 1 block diagram 19-5875; rev 1; 8/11 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/max2769b.related . e v a l u a t i o n k i t a v a i l a b l e general description the max2769b is a next-generation global navigation satellite system (gnss) receiver covering gps, glonass, galileo, and compass navigation satellite systems on a single chip. this single-conversion gnss receiver is designed to provide high performance for industrial and automotive applications. designed on maxims advanced, low-power sige bicmos process technology, the max2769b offers the highest performance and integration at a low cost. incorporated on the chip is the complete receiver chain, including a dual-input lna and mixer, followed by the image-rejected filter, pga, vco, fractional-n frequency synthesizer, crystal oscillator, and a multibit adc. the total cascaded noise figure of this receiver is as low as 1.4db. the max2769b completely eliminates the need for exter - nal if filters by implementing on-chip monolithic filters and requires only a few external components to form a com plete low-cost gps rf receiver solution. the max2769b is the most flexible receiver on the mar - ket. the integrated delta-sigma fractional-n frequency synthesizer allows programming of the if frequency within a 30hz (f xtal = 32mhz) accuracy while operat - ing with any reference or crystal frequencies that are available in the host system. the adc outputs cmos logic levels with 1 or 2 quantized bits for both i and q channels, or up to 3 quantized bits for the i channel. i and q analog outputs are also available. the max2769b is packaged in a 5mm x 5mm, 28-pin thin qfn package with an exposed paddle. applications automotive navigation systems location-enabled mobile handsets pnds (personal navigation devices) telematics (asset tracking, inventory management) marine/avionics navigation software gps laptops and netbooks features s aec-q100 automotive qualified s gps/glonass/galileo/compass systems s 40pf output clock drive capability s no external if saw or discrete filters required s programmable if frequency s fractional-n synthesizer with integrated vco supports wide range of reference frequencies s dual-input uncommitted lna for separate passive and active antenna inputs s 1.4db cascade noise figure s integrated crystal oscillator s integrated active antenna sensor s 2.7v to 3.3v supply voltage s small, 28-pin, rohs-compliant, thin qfn lead- free package (5mm x 5mm) lnaout v cc_rf mixin ld antflag i0 q0 q1 i1 clkout xtal lna2 pgm lna1 cpout v cc_vco sclk antbias v cc_adc 12 10 9 24 26 11 25 27 n.c. sdata 8 28 + v cc_cp 13 23 v cc_if 14 v ccd 22 19 17 16 3 5 18 4 6 15 7 20 2 21 1 n.c. shdn cs adc adc filter pll lna2 lna1 vco 90 0 3-wire interface idle max2769b for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 max2769b universal gps receiver v cc_ to ground .................................................... -0.3v to +4.2v other pins except lna_, mixin, xtal, and lnaout to ground ............................. -0.3v to +(operating v cc_ + 0.3v) maximum rf input power ............................................. +15dbm continuous power dissipation (t a = +70 n c) tqfn (derates 27mw/ n c above +70 n c) ................... 2500mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ......................... .......+300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40 n c to +85 n c, pgm = ground. registers are set to the default power-up states. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) (note 1) idle mode is a trademark of maxim integrated products, inc. caution! esd sensitive device parameter conditions min typ max units supply voltage 2.7 2.85 3.3 v supply current default mode, lna1 is active (note 2) 18 27 31 ma default mode, lna2 is active (note 2) 15 25 30.5 idle mode k , idle = low, shdn = high 5 shutdown mode, shdn = low 200 f a voltage drop at antbias from v cc_rf sourcing 20ma at antbias 0.2 v short-circuit protection current at antbias antbias is shorted to ground 57 ma active antenna detection current to assert logic-high at antflag 1.1 ma digital input and output digital input logic-high measure at the shdn pin 1.5 v digital input logic-low measure at the shdn pin 0.4 v * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede values quoted elsewhere in this data sheet.
????????????????????????????????????????????????????????????????? maxim integrated products 3 max2769b universal gps receiver ac electrical characteristics* (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40 n c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) (note 1) parameter conditions min typ max units cascaded rf performance rf frequency l1 band 1575.42 mhz noise figure lna1 input active, default mode (note 3) 1.4 db lna2 input active, default mode (note 3) 2.7 measured at the mixer input 10.3 out-of-band 3rd-order input intercept point measured at the mixer input (note 4) -7 dbm in-band mixer input referred 1db compression point measured at the mixer input -85 dbm mixer input return loss 10 db image rejection 25 db spurs at lna1 input lo leakage -101 dbm reference harmonics leakage -103 maximum voltage gain measured from the mixer to the baseband analog output 91 96 103 db variable gain range 55 59 db filter response passband center frequency fbw = 00 4 mhz fbw = 10 4 fbw = 01 9.27 passband 3db bandwidth fbw = 00 2.5 mhz fbw = 10 4.2 fbw = 01 9.66 lowpass 3db bandwidth fbw = 11 9 mhz stopband attenuation 3rd-order filter, bandwidth = 2.5mhz, measured at 4mhz offset 30 db 5th-order filter, bandwidth = 2.5mhz, measured at 4mhz offset 40 49.5 lna lna1 input power gain 19 db noise figure 0.83 db input ip3 (note 5) -1.1 dbm output return loss 10 db intput return loss 8 db * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede values quoted elsewhere in this data sheet.
????????????????????????????????????????????????????????????????? maxim integrated products 4 max2769b universal gps receiver ac electrical characteristics* (continued) (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40 n c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) (note 1) note 1: max2769b is production tested at t a = +25 n c and +85 n c. all min/max specifications are guaranteed by design and char - acterization from -40 n c to +85 n c, unless otherwise noted. default register settings are not production tested or guaran - teed. user must program the registers upon power-up. note 2: default, low-nf mode of the ic. lna choice is gated by the ant_flag signal. in the normal mode of operation without an active antenna, lna1 is active. if an active antenna is connected and ant_flag switches to 1, lna1 is automatically dis - abled and lna2 becomes active. pll is in an integer-n mode with f comp = f tcxo /16 = 1.023mhz and icp = 0.5ma. the complex if filter is configured as a 5th-order butterworth filter with a center frequency of 4mhz and bandwidth of 2.5mhz. output data is in a 2-bit sign/magnitude format at cmos logic levels in the i channel only. note 3: the lna output connects to the mixer input without a saw filter between them. note 4: two tones are located at 12mhz and 24mhz offset frequencies from the gps center frequency of 1575.42mhz at -60dbm/ tone. passive pole at the mixer output is programmed to be 13mhz. note 5: measured from the lna input to the lna output. two tones are located at 12mhz and 24mhz offset frequencies from the gps center frequency of 1575.42mhz at -60dbm per tone. parameter conditions min typ max units lna2 input power gain 13 db noise figure 1.14 db input ip3 (note 5) 1 dbm output return loss 19 db input return loss 11 db frequency synthesizer lo frequency range 0.2v < v tune < (v cc_ - 0.3v) 1550 1610 mhz lo tuning gain 57 mhz/v reference input frequency 8 44 mhz main divider ratio 36 32,767 reference divider ratio 1 1023 charge-pump current icp = 0 0.5 ma icp = 1 1 tcxo input buffer/output clock buffer frequency range 8 32 mhz output logic-level high (v oh ) with respect to ground, i oh = 10 f a (dc-coupled) 2 v output logic-level low (v ol ) with respect to ground, i ol = 10 f a (dc-coupled) 0.8 v capacitive slew current load = 10k w + 40pf, f clkout = 32mhz 11 ma output load 10||40 k i ||pf reference input level sine wave 0.5 v p-p clock output multiply/divide range /4, /2, /1 (x2, max input frequency of 16mhz) 4 x2 adc adc differential nonlinearity agc enabled, 3-bit output q 0.1 lsb adc integral nonlinearity agc enabled, 3-bit output q 0.1 lsb * the parametric values (min, typ, max limits) shown in the electrical characteristics table supersede values quoted elsewhere in this data sheet.
????????????????????????????????????????????????????????????????? maxim integrated products 5 max2769b universal gps receiver typical operating characteristics (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) cascaded receiver gain vs. pga gain code max2769b toc01 pga gain code (decimal format) cascaded receiver gain (db) 60 55 50 45 40 35 30 25 20 15 10 5 60 80 100 120 40 0 65 t a = +25c t a = -40c t a = +85c cascaded gain and noise figure vs. temperature max2769b toc02 temperature (c) noise figure (db) 60 35 10 -15 0.5 1.0 1.5 2.0 0 -40 85 cascaded gain 100 105 110 115 120 90 95 agc gain noise figure lna1 |s21| and |s12| vs. frequency max2769b toc03 frequency (ghz) lna1 |s21| and |s12| (db) 2.25 2.00 1.50 1.75 1.00 1.25 0.75 -40 -30 -20 -10 0 10 20 30 40 -50 0.50 2.50 |s21| |s12| lna1 gain and noise figure vs. lna1 bias digital code max2769b toc04 lna bias digital code (decimal) noise figure (db) lna1 gain (db) 14 13 2 3 4 6 7 8 9 10 11 5 12 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20 25 0 1 15 gain noise figure lna1 gain and noise figure vs. temperature max2769b toc05 temperature (c) noise figure (db) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 -40 85 lna1 gain (db) 18.8 19.0 19.2 19.4 19.6 17.8 18.6 18.4 18.2 18.0 lna bias = 1000 noise figure gain lna1 input 1db compression point vs. lna1 bias digital code max2769b toc06 lna bias digital code (decimal) lna1 input 1db compression point (dbm) 14 13 2 3 4 6 7 8 9 10 11 5 12 -12.5 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 -15.0 1 15
????????????????????????????????????????????????????????????????? maxim integrated products 6 max2769b universal gps receiver typical operating characteristics (continued) (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) lna2 |s21| and |s12| vs. frequency max2769b toc07 frequency (ghz) lna2 |s21| and |s12| (db) 2.25 2.00 0.75 1.00 1.25 1.50 1.75 -40 -30 -20 -10 0 10 20 30 -50 0.50 2.50 |s21| |s12| lna2 gain and noise figure vs. temperature max2769b toc08 temperature (c) noise figure (db) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -40 85 lna2 gain (db) 12.8 13.0 13.2 13.4 13.6 12.2 12.6 12.4 lna bias = 10 noise figure gain lna input return loss vs. frequency max2769b toc09 frequency (ghz) lna input return loss (db) 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 -40 -30 -20 -10 0 -50 1.0 2.2 lna1 lna2 lna output return loss vs. frequency max2769b toc10 frequency (ghz) lna output return loss (db) 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 -15 -10 -5 0 -20 1.0 2.2 lna1 lna2 mixer input referred ip1db vs. offset frequency max2769b toc11 offset frequency (mhz) mixer input referred ip1db (db) 250 200 150 100 50 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 0 300 p rf = -100dbm pga gain = 51db pga gain = 32db
????????????????????????????????????????????????????????????????? maxim integrated products 7 max2769b universal gps receiver typical operating characteristics (continued) (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) 1db cascaded noise figure desensitization vs. jammer frequency max2769b toc12a jammer frequency (mhz) jammer power (dbm) 925 900 875 850 825 -15 -10 -5 0 -20 800 950 max2769b toc12b 2050 2000 1950 1900 1850 1800 2100 mixer input referred noise figure vs. pga gain max2769b toc13 pga gain (db) mixer input referred noise figure (db) 55 45 35 25 15 8 10 12 14 16 6 5 65 3rd-order polyphase filter magnitude response vs. baseband frequency max2769b toc14 baseband frequency (mhz) magnitude (db) 9 8 7 6 5 4 3 2 -50 -40 -30 -20 -10 0 10 -60 1 10 fbw = 00b 5th-order polyphase filter magnitude response vs. baseband frequency max2769b toc15 baseband frequency (mhz) magnitude (db) 9 8 7 6 5 4 3 2 -60 -50 -40 -30 -20 -10 0 10 -70 1 10 fbw = 00b mixer input referred gain vs. pga gain code max2769b toc16 pga gain code (decimal format) mixer input referred gain (db) 60 55 50 45 40 35 30 25 20 15 10 5 40 60 80 100 20 0 65 t a = +25c t a = -40c t a = +85c
????????????????????????????????????????????????????????????????? maxim integrated products 8 max2769b universal gps receiver typical operating characteristics (continued) (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) 3rd-order polyphase filter vs. baseband frequency (fbw = 01) max2769b toc17 frequency (mhz) frequency response (db) 18 16 14 12 10 8 6 4 2 -50 -40 -30 -20 -10 0 10 -60 0 20 5th-order polyphase filter vs. baseband frequency (fbw = 01) max2769b toc18 frequency (mhz) frequency response (db) 18 16 14 12 10 8 6 4 2 -50 -40 -30 -20 -10 0 10 -60 0 20 3rd-order polyphase filter vs. baseband frequency (fbw = 10) max2769b toc19 frequency (mhz) frequency response (db) 18 16 14 12 10 8 6 4 2 -50 -40 -30 -20 -10 0 10 -60 0 20 5th-order polyphase filter vs. baseband frequency (fbw = 10) max2769b toc20 frequency (mhz) frequency response (db) 18 16 14 12 10 8 6 4 2 -50 -40 -30 -20 -10 0 10 -60 0 20 2-bit adc transfer curve max2769b toc21 differential voltage (v) code (decimal value) 0.8 0.6 -0.8 -0.6 -0.4 0 0.2 -0.2 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -0.5 -1.0 1.0 3-bit adc transfer curve max2769b toc22 differential voltage (v) code (decimal value) 0.8 0.6 -0.8 -0.6 -0.4 0 0.2 -0.2 0.4 1 2 3 4 5 6 7 0 -1.0 1.0
????????????????????????????????????????????????????????????????? maxim integrated products 9 max2769b universal gps receiver typical operating characteristics (continued) (max2769b ev kit, v cc_ = 2.7v to 3.3v, t a = -40c to +85 n c, pgm = ground. registers are set to the default power-up states. lna input is driven from a 50 i source. all rf measurements are done in the analog output mode with adc bypassed. pga gain is set to 51db gain by serial-interface word gainin = 111010. maximum if output load is not to exceed 10k i ||7.5pf on each pin. typical values are at v cc_ = 2.85v and t a = +25 n c, unless otherwise noted.) digital output cmos logic max2769b toc23 20ns/div clk 2v/div sign data 2v/div magnitude data 2v/div digital output differential logic max2769b toc24 40ns/div clk 1v/div sign+ 1v/div sign- 1v/div crystal oscillator frequency vs. digital tuning code max2769b toc25 digital tuning code (decimal) crystal oscillator frequency (khz) 28 24 20 16 12 8 4 16,367.90 16,367.95 16,368.00 16,368.05 16,368.10 16,367.85 0 32 t a = +25c t a = +85c t a = -40c crystal oscillator frequency variation vs. temperature max2769b toc26 temperature (c) crystal oscillator frequency variation (ppm) 60 35 10 -15 -8 -6 -4 -2 0 2 4 6 8 10 -10 -40 85 temperature sensor voltage vs. temperature max2769b toc27 temperature (c) temperature sensor voltage (v) 60 35 -15 10 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.4 -40 85 clock output driver with 40pf load max2769b toc28 20ns /div
???????????????????????????????????????????????????????????????? maxim integrated products 10 max2769b universal gps receiver typical application circuit table 1. component list designation quantity description c0, c9 2 0.47nf ac-coupling capacitors c1 1 27pf pll loop filter capacitor c2 1 0.47nf pll loop filter capacitor c3Cc8 6 0.1 f f supply voltage bypass capacitor c10, c11 2 10nf ac-coupling capacitor c12 1 0.47nf ac-coupling capacitor c13 1 0.1nf supply voltage bypass capacitor r1 1 20k i pll loop filter resistor lnaout v cc_rf mixin ld shdn antflag i0 q0 q1 i1 clkout xtal lna2 pgm lna1 cpout v cc_vco cs sclk antbias v cc_adc 12 10 9 24 26 11 25 27 n.c. sdata 8 28 + idle v cc_cp 13 23 v cc_if 14 v ccd 22 19 17 16 3 5 18 4 6 15 7 20 2 21 1 n.c. top view c3 c13 c8 c0 c9 c12 active antenna bias c4 c1 c2 c6 c7 c11 c10 c5 baseband output baseband clock reference input serial input adc adc filter pll lna2 lna1 vco 90 0 3-wire interface max2769b
???????????????????????????????????????????????????????????????? maxim integrated products 11 max2769b universal gps receiver pin description pin configuration pin name function 1 antflag active antenna flag logic output. a logic-high indicates that an active antenna is connected to the antbias pin. 2 lnaout lna output. the lna output is internally matched to 50 i . 3 antbias buffered supply voltage output. provides a supply voltage bias for an external active antenna. 4 v cc_rf rf section supply voltage. bypass to ground with 100nf and 100pf capacitors in parallel as close as possible to the pin. 5 mixin mixer input. the mixer input is internally matched to 50 i . 6 ld lock-detector cmos logic output. a logic-high indicates the pll is locked. 7 shdn operation control logic input. a logic-low shuts off the entire device. 8 sdata data digital input of 3-wire serial interface 9 sclk clock digital input of 3-wire serial interface. active when cs is low. data is clocked in on the rising edge of the sclk. max2769b tqfn top view 26 27 25 24 10 9 11 lnaout v cc_rf mixin ld 12 antflag i0 q0 q1 i1 clkout xtal 1 2 lna2 4 5 6 7 20 21 19 17 16 15 pgm lna1 cpout v cc_vco sclk antbias v cc_adc 3 18 28 8 n.c. ep sdata + 23 13 v cc_cp v cc_if 22 14 v ccd n.c. shdn cs idle
???????????????????????????????????????????????????????????????? maxim integrated products 12 max2769b universal gps receiver pin description (continued) pin name function 10 cs chip-select logic input of 3-wire serial interface. set cs low to allow serial data to shift in. set cs high when the loading action is completed. 11 v cc_vco vco supply voltage. bypass to ground with a 100nf capacitor as close as possible to the pin. 12 cpout charge-pump output. connect a pll loop filter as a shunt c and a shunt combination of series r and c (see the typical application circuit ). 13 v cc_cp pll charge-pump supply voltage. bypass to ground with a 100nf capacitor as close as possible to the pin. 14 v ccd digital circuitry supply voltage. bypass to ground with a 100nf capacitor as close as possible to the pin. 15 xtal xtal or reference oscillator input. connect to xtal or a dc-blocking capacitor if tcxo is used. 16 clkout reference clock output 17 q1 q-channel voltage outputs. bits 0 and 1 of the q-channel adc output or analog differential voltage output. 18 q0 19 v cc_adc adc supply voltage. bypass to ground with a 100nf capacitor as close as possible to the pin. 20 i0 i-channel voltage outputs. bits 0 and 1 of the i-channel adc output or analog differential voltage output. 21 i1 22 n.c. no connection. leave this pin unconnected. 23 v cc_if if section supply voltage. bypass to ground with a 100nf capacitor as close as possible to the pin. 24 idle operation control logic input. a logic-low enables the idle mode, in which the xtal oscillator is active, and all other blocks are off. 25 lna2 lna input port 2. this port is typically used with an active antenna. internally matched to 50 i . 26 pgm logic input. connect to ground to use the serial interface. a logic-high allows programming to 8 hard-coded by device states connecting sdata, cs , and sclk to supply or ground according to table 3. 27 lna1 lna input port 1. this port is typically used with a passive antenna. internally matched to 50 i (see the typical application circuit ). 28 n.c. no connection. leave this pin open. ep exposed pad. ultra-low-inductance connection to ground. place several vias to the pcb ground plane.
???????????????????????????????????????????????????????????????? maxim integrated products 13 max2769b universal gps receiver figure 1. schematic of the crystal oscillator in the max2679b ev kit detailed description integrated active antenna sensor the max2769b includes a low-dropout switch to bias an external active antenna. to activate the antenna switch output, set anten in the configuration 1 register to logic 1. this closes the switch that connects the antenna bias pin to v cc_rf to achieve a low 200mv dropout for a 20ma load current. a logic-low in anten disables the antenna bias. the active antenna circuit also features short-circuit protection to prevent the output from being shorted to ground. low-noise amplifier (lna) the max2769b integrates two low-noise amplifiers. lna1 is typically used with a passive antenna. this lna requires an ac-coupling capacitor. in the default mode, the bias current is set to 4ma, the typical noise figure and iip3 are approximately 0.8db and -1.1dbm, respectively. lna2 is typically used with an active antenna. the lna2 is internally matched to 50. and requires a dc-blocking capacitor. bits lnamode in the configuration 1 register control the modes of the two lnas. see table 6 and table 7 for the lna mode settings. mixer the max2769b includes a quadrature mixer to output low-if or zero if i and q signals. the quadrature mixer is internally matched to 50 i and requires a low-side lo injection. the output of the lna and the input of the mixer are brought off-chip to facilitate the use of a saw filter. programmable gain amplifier (pga) the max2769b integrates a baseband programmable gain amplifier that provides 59db of gain control range. the pga gain can be programmed through the serial interface by setting bits gainin in the configuration 3 register. set bits 12 and 11 (agcmode) in the configuration 2 register to 10 to control the gain of the pga directly from the 3-wire interface. automatic gain control (agc) the max2769b provides a control loop that automatically programs pga gain to provide the adc with an input power that optimally fills the converter and establishes a desired magnitude bit density at its output. an algorithm operates by counting the number of magnitude bits over 512 adc clock cycles and comparing the magnitude bit count to the reference value provided through a control word (gainref). the desired magnitude bit density is expressed as a value of gainref in a decimal format divided by the counter length of 512. for example, to achieve the magnitude bit density of 33%, which is opti - mal for a 2-bit converter, program the gainref to 170, so that 170/512 = 33%. baseband filter the baseband filter of the receiver can be programmed to be a lowpass filter or a complex bandpass filter. the lowpass filter can be configured as a 3rd-order butterworth filter for a reduced group delay by setting bit f3or5 in the configuration 1 register to be 1 or a 5th-order butterworth filter for a steeper out-of-band rejection by setting the same bit to be 0. the two-sided 3db corner bandwidth can be selected to be 2.5mhz, 4.2mhz, 9.66mhz, or by programming bits fbw in the configuration 1 register. when the complex filter is enabled by changing bit fcenx in the configuration 1 register to 1, the lowpass filter becomes a bandpass filter and the center frequency can be programmed by bits fcen and fcenmsb in the configuration 1 register. clkout 10nf 16 15 xtal 23pf baseband clock max2769b
???????????????????????????????????????????????????????????????? maxim integrated products 14 max2769b universal gps receiver synthesizer the max2769b integrates a 20-bit sigma-delta fractional- n synthesizer allowing the device to tune to a required vco frequency with an accuracy of approximately q 30hz. the synthesizer includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer portion main divider with a divisor range programmable from 36 to 32767, and also a 20-bit fractional portion main divider. the reference divider is programmable by bits rdiv in the pll integer division ratio register (see table 11 ), and can accommodate ref - erence frequencies from 8mhz to 32mhz. the reference divider needs to be set so the comparison frequency falls between 0.05mhz to 32mhz. the pll loop filter is the only external block of the syn - thesizer. a typical pll filter is a classic c-r-c network at the charge-pump output. the charge-pump output sink and source current is 0.5ma by default, and the lo tuning gain is 57mhz/v. as an example, see the typical application circuit for the recommended loop- filter component values for f comp = 1.023mhz and loop bandwidth = 50khz. the desired integer and fractional divider ratios can be calculated by dividing the lo frequency (f lo ) by f comp . f comp can be calculated by dividing the tcxo frequency (f tcxo ) by the reference division ratio (rdiv). for exam - ple, let the tcxo frequency be 20mhz, rdiv be 1, and the nominal lo frequency be 1575.42mhz. the following method can be used when calculating divider ratios sup - porting various reference and comparison frequencies: tcxo lo comp f 20mhz comparison frequency 20mhz rdiv 1 f 1575.42mhz lo frequency divider 78.771 f 20mhz = = = = = = integer divider = 78(d) = 000 000 0100 1110 (binary) fractional divider = 0.771 x 220 = 808452 (decimal) = 1100 0101 0110 0000 0100 in the fractional mode, the synthesizer should not be operated with integer division ratios greater than 251. crystal oscillator the max2769b includes an on-chip crystal oscillator. a parallel mode crystal is required when the crystal oscilla - tor is being used. it is recommended that an ac-coupling capacitor be used in series with the crystal and the xtal pin to optimize the desired load capacitance and to center the crystal-oscillator frequency. take the para - sitic loss of interconnect traces on the pcb into account when optimizing the load capacitance. for example, the max2769b ev kit utilizes a 16.368mhz crystal that is designed for a 12pf load capacitance. a series capaci - tor of 23pf is used to center the crystal oscillator frequen - cy, see figure 1 . in addition, the 5-bit serial-interface word, xtalcap in the pll configuration register, can be used to vary the crystal-oscillator frequency electroni - cally. the range of the electronic adjustment depends on how much the chosen crystal frequency can be pulled by the varying capacitor. the frequency of the crystal oscillator used on the max2769b ev kit has a range of approximately 200hz. the max2769b provides a reference clock output. the frequency of the clock can be adjusted to crystal-oscilla - tor frequency, a quarter of the oscillator frequency, a half of the oscillator frequency (f xtal p 16mhz), or twice the oscillator frequency, by programming bits refdiv in the pll configuration register. table 2. output data format integer value sign/magnitude unsigned binary twos complement binary 1b 2b 3b 1b 2b 3b 1b 2b 3b 7 0 01 011 1 11 111 0 01 011 5 0 01 010 1 11 110 0 01 010 3 0 00 001 1 10 101 0 00 001 1 0 00 000 1 10 110 0 00 000 -1 1 10 100 0 01 011 1 11 111 -3 1 10 101 0 01 010 1 11 110 -5 1 11 110 0 00 001 1 10 101 -7 1 11 111 0 00 000 1 10 100
???????????????????????????????????????????????????????????????? maxim integrated products 15 max2769b universal gps receiver figure 2. adc quantization levels for 2- and 3-bit cases adc the max2769b features an on-chip adc to digitize the downconverted gps signal. the maximum sampling rate of the adc is approximately 50msps. the sampled output is provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default and also can be configured as a 1-bit or 2-bit in both i and q channels, or 1-bit, 2-bit, or 3-bit in the i channel only. the adc supports the digital outputs in three different formats: the unsigned binary, the sign and magnitude, or the twos complement format by setting bits format in configuration register 2. msb bits are output at i1 or q1 pins and lsb bits are output at i0 or q0 pins, for i or q channel, respectively. in the case of 3-bit, output data format is selected in the i channel only, the msb is output at i1, the second bit is at i0, and the lsb is at q1. figure 2 illustrates the adc quantization levels for 2-bit and 3-bit cases and also describes the sign/magnitude data mapping. the variable t = 1 designates the location of the magnitude threshold for the 2-bit case. adc fractional clock divider a 12-bit fractional clock divider is located in the clock path prior to the adc and can be used to generate the adc clock that is a fraction of the reference input clock. in a fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. for example, if the fractional output clock is 4.5 times slower than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and divide-by-5 periods. the fractional division ratio is given by: f out /f in = l count /(4096 - m count + l count ) where l count and m count are the 12-bit counter val - ues programmed through the serial interface. 1 2 3 4 5 6 7 -1 -2 -3 -4 -5 -6 -7 000 00 01 10 11 t = 1 111 110 101 100 001 010 011
???????????????????????????????????????????????????????????????? maxim integrated products 16 max2769b universal gps receiver dsp interface gps data is output from the adc as the four logic sig nals (bit 0 , bit 1 , bit 2 , and bit 3 ) that represent sign/magnitude, unsigned binary, or twos complement binary data in the i (bit 0 and bit 1 ) and q (bit 2 and bit 3 ) channels. the resolution of the adc can be set up to 3 bits per channel. for example, the 2-bit i and q data in sign/magnitude format is mapped as follows: bit 0 = i sign , bit 1 = i mag , bit 2 = q sign , and bit 3 = q mag . the data can be serial - ized in 16-bit segments of bit 0 , followed by bit 1 , bit 2 , and bit 3 . the number of bits to be serialized is controlled by the bits strmbits in the configuration 3 register. this selects between bit 0 ; bit 0 and bit 1 ; bit 0 and bit 2 ; and bit 0 , bit 1 , bit 2 , and bit 3 cases. if only bit 0 is serialized, the data stream consists of bit 0 data only. if a serialization of bit 0 and bit 1 (or bit 2 ) is selected, the stream data pattern consists of 16 bits of bit 0 data followed by 16 bits of bit 1 (or bit 2 ) data, which, in turn, is followed by 16 bits of bit 0 data, and so on. in this case, the serial clock must be at least twice as fast as the adc clock. if a 4-bit serialization of bit 0 , bit 1 , bit 2 , and bit 3 is chosen, the serial clock must be at least four times faster than the adc clock. the adc data is loaded in parallel into four holding registers that correspond to four adc outputs. holding registers are 16 bits long and are clocked by the adc clock. at the end of the 16-bit adc cycle, the data is transferred into four shift registers and shifted serially to the output during the next 16-bit adc cycle. shift regis - ters are clocked by a serial clock that must be chosen fast enough so that all data is shifted out before the next set of data is loaded from the adc. an all-zero pattern follows the data after all valid adc data are streamed to the output. a datasync signal is used to signal the beginning of each valid 16-bit data slice. in addition, there is a time_sync signal that is output every 128 to 16,384 cycles of the adc clock. figure 3. dsp interface top-level connectivity and control signals strm_en strm_start strm_stop strm_count<2:0> dieid<1:0> strm_bits<1:0> frm_count<27:0> stamp_en dat_syncen time_syncen strm_rst l_cnt<11:0> m_cnt<11:0> refdiv<1:0> bit 0 pin 21 pin 20 pin 17 pin 18 bit 1 bit 2 bit 3 data_out clk_ser data_sync time_sync adc i q clk_ad c clk_ser control signals from 3-wire interface strm_en output driver strm_en clk_in clk_out through /2 /4 x2 ref/xtal pin 15 adcclk_sel serclk_sel frclk_sel
???????????????????????????????????????????????????????????????? maxim integrated products 17 max2769b universal gps receiver preconfigured device states when a serial interface is not available, the device can be used in preconfigured states that dont require pro - gramming through the serial interface. connecting the pgm pin to logic-high and sclk, sdata, and cs pins to either logic-high or low sets the device in one of the preconfigured states according to table 3 . power-on reset (por) the max2769b incorporates power-on reset circuitry to ensure that register settings are loaded upon power-up. to ensure proper operation, the rising edge of pgm must occur no sooner than when v cc_ reaches 90% of its final nominal value; see figure 4 for details. serial interface, address, and bit assignments a serial interface is used to program the max2769b for configuring the different operating modes. the serial interface is controlled by three signals: sclk (serial clock), cs (chip select), and sdata (serial data). the control of the pll, agc, test, and block selection is performed through the serial-interface bus from the baseband controller. a 32-bit word, with the msb (d27) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. the timing of the interface signals is shown in figure 5 and table 4 along with typical values for setup and hold time requirements. table 3. preconfigured device states figure 4. v cc_ power-on reset device state device electrical characteristics 3-wire control pins reference frequency (mhz) reference division ratio main division ratio i and q or i only number of iq bits i and q logic level if center frequency (mhz) if filter bw (mhz) if filter order sclk data cs 0 16.368 16 1536 i 1 differential 4.092 2.5 5th 0 0 0 1 16.368 16 1536 i 1 differential 4.092 2.5 3rd 0 0 1 2 16.368 16 1536 i 2 cmos 4.092 2.5 5th 0 1 0 3 32.736 32 1536 i 2 cmos 4.092 2.5 5th 0 1 1 4 19.2 96 7857 i 2 cmos 4.092 2.5 5th 1 0 0 5 27.456 26 1488 i 3 cmos 4.092 4.2 5th 1 0 1 6 16.368 16 1536 i 3 cmos 4.092 4.2 5th 1 1 0 7 27.456 26 1508 i 3 cmos 9.27075 9.66 5th 1 1 1 90% time (s) time (s) pgm = 0 pgm pgm rising edge anytime after v cc_ has reached 90% of its nominal value. 0% v cc_ 100%
???????????????????????????????????????????????????????????????? maxim integrated products 18 max2769b universal gps receiver figure 5. 3-wire timing diagram table 4. serial-interface timing requirements table 5. default register settings overview symbol parameter typ value units t css falling edge of cs to rising edge of the first sclk time. 10 ns t ds data to serial-clock setup time. 10 ns t dh data to clock hold time. 10 ns t ch serial clock pulse-width high. 25 ns t cl clock pulse-width low. 25 ns t csh last sclk rising edge to rising edge of cs . 10 ns t csw cs high pulse width. 1 clock register name address (a3:a0) data conf1 0000 configures rx and if sections, bias settings for individual blocks. conf2 0001 configures agc and output sections. conf3 0010 configures support and test functions for if filter and agc. pllconf 0011 pll, vco, and clk settings. div 0100 pll main and reference division ratios, other controls. fdiv 0101 pll fractional division ratio, other controls. strm 0110 dsp interface number of frames to stream. clk 0111 fractional clock-divider values. test1 1000 reserved for test mode. test2 1001 reserved for test mode. sclk cs sdata data msb data lsb addr msb addr lsb t csh t csw t cl t dh t ch t css t ds
???????????????????????????????????????????????????????????????? maxim integrated products 19 max2769b universal gps receiver detailed register definitions table 6. default register settings table 7. configuration 1 (address: 0000) register name address (a3:a0) power-on reset, pgm = 0 (hex) preconfigured device state , pgm = 1 (hex) 0 1 2 3 4 5 6 7 conf1 0000 a2919a3 a2919a3 a2919a3 a2919a7 a2919a3 a2919a3 a293573 a293573 a29b26b conf2 0001 055028c 055121c 055028c 055121c 055028c 055028c 855030c 855030c 855030c conf3 0010 eafe1dc eafe1dc eafe1dc eafe1dc eafe1dc eafe1dc eafe1dc eafe1dc eafe1dc pllconf 0011 9ec0008 9ec0008 9ec0008 9ec0008 9ec0008 9ec0008 9ec0008 9ec0008 9ec0008 div 0100 0c00080 0c00080 0c00080 0c00080 0c00100 3d62300 0ba00d0 0c00080 0bc80d0 fdiv 0101 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070 strm 0110 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 clk 0111 10061b2 10061b2 10061b2 10061b2 10061b2 10061b2 10061b2 10061b2 10061b2 test1 1000 1e0f401 1e0f401 1e0f401 1e0f401 1e0f401 1e0f401 1e0f401 1e0f401 1e0f401 test2 1001 28c0402 28c0402 28c0402 28c0402 28c0402 28c0402 28c0402 28c0402 7cc0403 data bit location default value (pgm = 0) description chipen 27 1 chip enable. set 1 to enable the device and 0 to disable the entire device except the serial bus. idle 26 0 idle enable. set 1 to put the chip in the idle mode and 0 for operating mode. reserved 25:22 1000 reserved 21:20 10 reserved 19:18 10 reserved 17:16 01 mixpole 15 0 mixer pole selection. set 1 to program the passive filter pole at mixer output at 36mhz, or set 0 to program the pole at 13mhz. lnamode 14:13 00 lna mode selection, d14:d13 = 00: lna selection gated by the antenna bias circuit, 01: lna2 is active; 10: lna1 is active; 11: both lna1 and lna2 are off. mixen 12 1 mixer enable. set 1 to enable the mixer and 0 to shut down the mixer. anten 11 1 antenna bias enable. set 1 to enable the antenna bias and 0 to shut down the antenna bias. fcen 10:5 001101 if center frequency programming. default for f center = 3.092mhz, bw = 2.5mhz. the msb of fcen is located in register test mode 2 (table 16). 001101 = 3.092mhz, 001011 = 4.092mhz, 010011 = 10.0mhz fbw 4:3 00 if filter center bandwidth selection. d4:d3 = 00: 2.5mhz; 10: 4.2mhz; 01: 9.66mhz; 11: reserved. f3or5 2 0 filter order selection. set 0 to select the 5th-order butterworth filter. set 1 to select the 3rd- order butterworth filter. fcenx 1 1 polyphase filter selection. set 1 to select complex bandpass filter mode. set 0 to select lowpass filter mode. fgain 0 1 if filter gain setting. set 0 to reduce the filter gain by 6db.
???????????????????????????????????????????????????????????????? maxim integrated products 20 max2769b universal gps receiver table 8. configuration 2 (address: 0001) table 9. configuration 3 (address: 0010) data bit location default value (pgm = 0) description iqen 27 0 i and q channels enable. set 1 to enable both i and q channels and 0 to enable i channel only. gainref 26:15 170d agc gain reference value expressed by the number of msb counts (magnitude bit density). 10101010 = 234 magnitude bit density reference, 1010100 = 84 magnitude bit density reference, 100111010 = 314 magnitude bit density reference. reserved 14:13 00 reserved. agcmode 12:11 00 agc mode control. set d12:d11 = 00: independent i and q; 01: reserved; 10: gain is set directly from the serial interface by gainin; 11: reserved. format 10:9 01 output data format. set d10:d9 = 00: unsigned binary; 01: sign and magnitude; 1x: twos complement binary. bits 8:6 010 number of bits in the adc. set d8:d6 = 000: 1 bit, 001: reserved; 010: 2 bits; 011: reserved, 100: 3 bits. drvcfg 5:4 00 output driver configuration. set d5:d4 = 00: cmos logic, 01: reserved; 1x: analog outputs. reserved 3 1 reserved 2 0 dieid 1:0 00 identifies a version of the ic. data bit location default value (pgm = 0) description gainin 27:22 111010 pga gain value programming from the serial interface in steps of db per lsb. 000000 = pga gain set to 0db, 101011 = 42db, 101100 = 43db, 101110 = 45db, 111010 = 57db, 111111 = 62db. reserved 21 1 hiloaden 20 0 set 1 to enable the output driver to drive high loads. reserved 19 1 reserved 18 1 reserved 17 1 reserved 16 1 fhipen 15 1 highpass coupling enable. set 1 to enable the highpass coupling between the filter and pga, or 0 to disable the coupling. reserved 14 1 reserved 13 1 reserved 12 0 strmen 11 0 dsp interface for serial streaming of data enable. this bit configures the ic such that the dsp interface is inserted in the signal path. set 1 to enable the interface or 0 to disable the interface.
???????????????????????????????????????????????????????????????? maxim integrated products 21 max2769b universal gps receiver table 9. configuration 3 (address: 0010) (continued) table 10. pll configuration (address: 0011) data bit location default value (pgm = 0) description strmstart 10 0 the positive edge of this command enables data streaming to the output. it also enables clock, data sync, and frame sync outputs. strmstop 9 0 the positive edge of this command disables data streaming to the output. it also disables clock, data sync, and frame sync outputs. reserved 8:6 111 strmbits 5:4 01 number of bits streamed. d5:d4 = 00: reserved; 01: 1 msb, 1 lsb; 10: reserved, q msb; 11: 1 msb, 1 lsb, q msb, q lsb. stampen 3 1 the signal enables the insertion of the frame number at the beginning of each frame. if disabled, only the adc data is streamed to the output. timesyncen 2 1 this signal enables the output of the time sync pulses at all times when streaming is enabled by the strmen command. otherwise, the time sync pulses are available only when data streaming is active at the output, for example, in the time intervals bound by the strmstart and strmstop commands. datsyncen 1 0 this control signal enables the sync pulses at the datasync output. each pulse is coincident with the beginning of the 16-bit data word that corresponds to a given output bit. strmrst 0 0 this command resets all the counters irrespective of the timing within the stream cycle. data bit location default value (pgm = 0) description reserved 27 1 reserved 26 0 reserved 25 0 refouten 24 1 clock buffer enable. set 1 to enable the clock buffer or 0 to disable the clock buffer. reserved 23 1 refdiv 22:21 11 clock output divider ratio. set d22:d21 = 00: clock frequency = xtal frequency x 2; 01: clock frequency = xtal frequency/4; 10: clock frequency = xtal frequency/2; 11: clock frequency = xtal. ixtal 20:19 01 current programming for xtal oscillator/buffer. set d20:d19 = 00: reserved; 01: buffer normal current; 10: reserved; 11: oscillator high current. reserved 18:14 10000 ldmux 13:10 0000 pll lock-detect enable.
???????????????????????????????????????????????????????????????? maxim integrated products 22 max2769b universal gps receiver table 10. pll configuration (address: 0011) (continued) table 11. pll integer division ratio (address 0100) table 12. pll division ratio (address 0101) table 13. reserved (address 0110) data bit location default value (pgm = 0) description icp 9 0 charge-pump current selection. set 1 for 1ma and 0 for 0.5ma. pfden 8 0 set 0 for normal operation or 1 to disable the pll phase frequency detector. reserved 7 0 reserved 6:4 000 int_pll 3 1 pll mode control. set 1 to enable the integer-n pll or 0 to enable the fractional-n pll. pwrsav 2 0 pll power-save mode. set 1 to enable the power-save mode or 0 to disable. reserved 1 0 reserved 0 0 data bit location default value (pgm = 0) description ndiv 27:13 1536d pll integer division ratio. rdiv 12:3 16d pll reference division ratio. reserved 2:0 000 data bit location default value (pgm = 0) description fdiv 27:8 80000h pll fractional divider ratio. reserved 7:0 01110000 data bit location default value (pgm = 0) description reserved 27:0 8000000h
???????????????????????????????????????????????????????????????? maxim integrated products 23 max2769b universal gps receiver table 14. clock fractional division ratio (address 0111) table 15. test mode 1 (address 1000) table 16. test mode 2 (address 1001) applications information the lna and mixer inputs require careful consideration in matching to 50 i lines. proper supply bypassing, grounding, and layout are required for reliable perfor - mance from any rf circuit. layout issues the max2769b ev kit can be used as a starting point for layout. for best performance, take into consideration grounding and routing of rf, baseband, and power- supply pcb proper line. make connections from vias to the ground plane as short as possible. on the high- impedance ports, keep traces short to minimize shunt capacitance. ev kit gerber files can be requested at www.maxim-ic.com . power-supply layout to minimize coupling between different sections of the ic, a star power-supply routing configuration with a large decoupling capacitor at a central v cc_ node is recom - mended. the v cc_ traces branch out from this node, each going to a separate v cc_ node in the circuit. place a bypass capacitor as close as possible to each supply pin this arrangement provides local decoupling at each v cc_ pin. use at least one via per bypass capacitor for a low-inductance ground connection. do not share the capacitor ground vias with any other branch. refer to maxims wireless and rf application notes for more information. data bit location default value (pgm = 0) description l_cnt 27:16 256d sets the value for the l counter. 000100000000 = 256 fractional clock divider, 100000000000 = 2048 fractional clock divider. m_cnt 15:4 1563d sets the value for the m counter. 011000011011 = 1563 fractional clock divider, 100000000 = 2048 fractional clock divider. fclkin 3 0 fractional clock divider. set 1 to select the adc clock to come from the fractional clock divider, or 0 to bypass the adc clock from the fractional clock divider. adcclk 2 0 adc clock selection. set 0 to select the adc and fractional divider clocks to come from the reference divider/multiplier. reserved 1 1 mode 0 0 dsp interface mode selection. data bit location default value (pgm = 0) description reserved 27:0 1e0f401 data bit location default value (pgm = 0) description reserved 27:1 28c0402 fcenmsb 0 0 when combined with fcen, this bit represents the msb of a 7-bit fcen word.
???????????????????????????????????????????????????????????????? maxim integrated products 24 max2769b universal gps receiver ordering information chip information process: sige bicmos + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package max2769beti/v+ -40 n c to +85 n c 28 tqfn-ep* package type package code outline no. land pattern no. 28 tqfn-ep t2855+3 21-0140 90-0023
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 25 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max2769b universal gps receiver revision history revision number revision date description pages changed 0 5/11 initial release 1 8/11 corrected part number in ordering information section. 24

▲Up To Search▲

Price & Availability of MAX2769BETIV

	To Download MAX2769BETIV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .